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Bit Error
Rate Tester (BERT)
For low-level testing of physical links, the extended physical layer verification
system combines bit error rate testing, eye pattern signal synchronization
and versatile pattern generation in a single instrument.
Product Features and Benefits
* Create Eye Pattern Signals for Jitter Analysis
* Send Legal or Illegal 10B Patterns
* Bit Error Rate Test at 1.0625, 1.25, 2.125 & 2.5 Gbps- supports
line rates up to 4Gb/s
* Script with Predefined and Custom Elements
* Define in 8B or 10B
* Trigger-In to Start or Stop Data Generation
The Extended Physical Layer Verification System combines bit error rate
testing, eye pattern signal synchronization and versatile pattern generation
in a single instrument. This is a front line tool for physical layer verification
of up to 4Gb/s Fibre Channel and Gigabit Ethernet devices.
Verifying data integrity is key to insuring the performance and reliability
of Gigabit-rate networks and systems. Physical layer testing requires
worst-case data loading and bit-by-bit data checking with results presented
in an industry accepted format like BER. The Xgig BERT verifies data integrity
by sending industry-standard worst-case data patterns through network
devices.
These data patterns are designed to stress the physical layer of the system,
with patterns specifically developed to check frequency response, data
dependencies and network interface components. With bit-by-bit comparison,
any difference between the transmitted and received data is detected,
counted and captured for additional analysis. Unique data patterns can
be created to meet special test requirements.
The Xgig BERT is protocol aware for Gigabit Ethernet and Fibre Channel.
The unit recognizes data modifications allowed by devices on the link
and does not report them as errors. The Xgig BERT can also greatly reduce
manufacturing test times for test hubs, host bus adapters, Fibre Channel
RAIDs, and other active or passive devices by stressing all of the components
in the data path. Eliminate the hours of test time looking for a data-dependent
error which happened only rarely in a normal traffic stream.
Since 1997, Gillaspy Associates has built
a solid reputation for developing strong relationships with our customers
by providing quality solutions and ongoing support.
Downloads
Xgig BERT Bit Error Rate
Tester Datasheet PDF
Application Note- Using
the BERT for DWDM Installation 2.26.03
Training Courses
Gillaspy currently offers the following training courses:
SAS
ML270 - Serial Attached
SCSI Architecture & Instrumentation
Fibre Channel
ML250 - Fibre Channel
Systems Architecture & Instrumentation
ML350 - In-depth Fibre Channel
Analysis
iSCSI
ML280 - iSCSI Architecture
and Instrumentation
FCIP
ML240 - Introduction to Fibre
Channel Over IP (FCIP)
MCE: Medusa Certified Engineer
MC100 - Xgig Analyzer
MC125 - NetWisdom SAN
Performance Monitoring System
SATA
Serial ATA Architecture
IO Bus
PCI™ Architecture
PCI™ Overview
PCI-X™ Architecture
PCI-X™ Overview
PCI Express ™
Architecture
PCI-Express™
Overview
Intel Pentium
4/m/Xeon
USB Architecture (Core
Topics)
USB Architecture (LS/FS
Only)
USB Architecture (HS
Only)
Contact Gillaspy Assocates at 805-987-1959 to schedule an on-site class.
